Combinational Circuits MCQ Quiz - Objective Question with Answer for Combinational Circuits - Download Free PDF

A half adder circuit is made up of an AND gate with an XOR gate as shown below:

• A half adder is also known as XOR gate because XOR is applied to both inputs to produce the sum
• Half adder can add only two bits (A and B) and has nothing to do with the carry
• If the input to a half adder has a carry, then it will neglect it and adds only the A and B bits
• That means the binary addition process is not complete and that's why it is called a half adder

Sum (S) = A⊕B, Carry = A.B

The correct answer is: The encoder will output the binary code for the highest priority active input.

Explanation:

A priority encoder is a combinational circuit that:

• Accepts multiple input lines, but only one output is generated at a time.

• If two or more inputs are active simultaneously, the input with the highest priority (usually the one with the highest input number) is encoded and reflected at the output.

This ensures unambiguous output even when multiple inputs are high.

🔍 Example:

For a 4-to-2 priority encoder with inputs D3 to D0 (D3 has highest priority):

Explanation:

3-bit Gray Counter Controlled Multiplexer

Definition: A 3-bit Gray counter is a type of binary counter in which two successive values differ in only one bit. This counter is used to control the output of a multiplexer, which selects one of several input signals and forwards the selected input to a single output line.

Working Principle: In the given scenario, the 3-bit Gray counter is used to control the multiplexer’s output. The counter starts from an initial state of 000 and goes through a sequence of states where only one bit changes at a time. The output of the multiplexer is pulled high when it is not enabled.

The Gray code sequence for a 3-bit counter is as follows:

• 000
• 001
• 011
• 010
• 110
• 111
• 101
• 100

Sequence Analysis:

With the initial state of the counter being 000, the multiplexer will follow the Gray code sequence mentioned above. The multiplexer is enabled only for certain states, and the output is high (1) when it is not enabled. Let’s analyze the sequence step-by-step:

1. 000: Multiplexer selects I0.
2. 001: Multiplexer is not enabled, output is 1.
3. 011: Multiplexer is not enabled, output is 1.
4. 010: Multiplexer selects I1.
5. 110: Multiplexer selects I3.
6. 111: Multiplexer is not enabled, output is 1.
7. 101: Multiplexer is not enabled, output is 1.
8. 100: Multiplexer selects I2.

Based on this analysis, the output sequence of the circuit is:

I0, 1, 1, I1, I3, 1, 1, I2

Correct Option Analysis:

The correct option is:

Option 1: I0, 1, 1, I1, I3, 1, 1, I2

This option correctly describes the output sequence of the multiplexer controlled by the 3-bit Gray counter

The correct answer is a type of circuit.
Key Points

• A logic gate is a fundamental building block of digital circuits.
• It performs a basic logical function, such as AND, OR, NOT, NAND, NOR, XOR, and XNOR.
• Logic gates process one or more input signals to produce an output signal based on a certain logic.
• They are used in various electronic devices to perform computations and make decisions.
• Logic gates are implemented using diodes, transistors, and other electronic components.

Additional Information

• AND Gate
  • An AND gate outputs true (1) only if all its inputs are true (1).
  • It performs a logical conjunction operation.
• OR Gate
  • An OR gate outputs true (1) if at least one of its inputs is true (1).
  • It performs a logical disjunction operation.
• NOT Gate
  • A NOT gate outputs the inverse of its input.
  • If the input is true (1), the output is false (0), and vice versa.

Decoder:

The decoder is a combinational ckt, that convert Binary Coded information into Familiar, representation like the decimal, octal, Hexadecimal, etc.

The decoder has ‘n’ no of i/p & less than equal to 2n O/P

i.e., \(\begin{array}{*{20}{c}} {n \le }&{{2^n}}\\ {\frac{I}{P}}&{\frac{O}{P}} \end{array}\)

For 4 input lines n = 4

Maximum output lines = 2⁴ = 16

Additional Information

Multiplexer (MUX) is defined as:

Based on the select line, it selects the input & produces its output. i.e., at a time one input is taken to get output.

“MUX” is also known as

→ Data selector

→ Parallel to serial converter

→ Many to one circuit.

→ Universal logic Ckt.

Combinational Logic circuits are circuits for which the present output depends only on the present input, i.e. there is no memory element to store the past output.

A combinational circuit can have ‘n’ number of inputs and ‘m’ number of outputs as shown:

Combinational circuits are:

• Multiplexer/Demultiplexer
• Encoder/Decoder
• Adders
• Subtractors
• Code Converters

Multiplexers:

• A multiplexer is Many to one data selector.
• A multiplexer selects one of the many data available at its input depending on the bits on the select line.
• For 2m inputs, there are m select lines that determine which input is to be connected to the output.

In a sequential circuit, the output depends on both the present and the past values. The circuit diagram is as shown:

Examples of sequential circuits:

• Shift Registers
• Flip flops
• Counters

Concept:

In a 4 × 1 MUX

Truth-Table

Y = Output = S̅₁ S̅₀ I₀ + S̅₁ S₀ I₁ + S₁ S̅₀ I₂ + S₁ S₀ I₃

MUX contains AND gate followed by OR gate

Calculation:

By re-drawing circuit diagram

∴ I₀ = 0, I₁ = 1, I₂ = 1, I₃ = 0 & (P = S₁, Q = S₀)

Now output of 4 × 1 MUX is

Y = F = (P̅ Q̅) 0 + (P̅ Q)1 + (P Q̅) 1 + (P Q)0

∴ F = P Q̅ + P̅ Q = P ⊕ Q

∴ F = XOR (P, Q) 

The correct option is 1

Concept:

Multiplexer: It is a device that combines several inputs and outputs them into a single line.

Demultiplexer: It is a device that reverses the process of multiplexer i.e. it converts data from a single input line to multiple output lines.

NAND Gate:

• NAND gate represents the complement of the AND operation.
• The graphic symbol for the NAND gate consists of an AND symbol with a bubble on the output, denoting that a complement operation is performed on the output of the AND gate. 
• The logic NAND function can be expressed by the Boolean expression of, A.B.

​

Analysis:

Given A = 1100 and B = 1010

∴ The output will be 0111.

Half adder circuit have two inputs and two outputs (sum and carry).

A half adder circuit is made up of an AND gate with an XOR gate as shown below:

• A half adder is also known as XOR gate because XOR is applied to both inputs to produce the sum
• Half adder can add only two bits (A and B) and has nothing to do with the carry
• If the input to a half adder has a carry, then it will neglect it and adds only the A and B bits
• That means the binary addition process is not complete and that's why it is called a half adder

Sum (S) = A⊕B, Carry = A.B

Combinational Logic circuits are circuits for which the present output depends only on the present input, i.e. there is no memory element to store the past output.

A combinational circuit can have ‘n’ number of inputs and ‘m’ number of outputs as shown:

Combinational circuits are:

• Multiplexer/Demultiplexer
• Encoder/Decoder
• Adders
• Subtractors
• Code Converters

In a sequential circuit, the output depends on both the present and the past values. The circuit diagram is as shown:

Examples of sequential circuits:

• Shift Registers
• Flip flops
• Counters

Concept:

The output of a NOR gate will be at logic 1 when all the input is at logic 0.

• NOR gate is the output (f).
• For the NOR gate whenever there is input(high), It gives Zero.
• The NOR gate is connected with \(D_1,D_4 and D_7\) only, so we have to look after those input only.

Hence, the output of the given circuit is given as:

F = ∑m (0, 2, 3, 5, 6)

Concept: 

For a 2 × 1 MUX is shown above, the output function F is expressed as:

F = S̅₁ I₀ + S₁I₁

i.e. when S₁ = 0, I₀ is transmitted to the output.

And when S₁ = 1, I₁ is transmitted to the output.

Analysis:

The given circuit is redrawn as:

F₁ = S̅₁ w + S₁ w̅

F₁ = S₁ ⊕ w

Now, the required function f will be:

F₂ = F = S̅₂F₁ + S₂F̅₁

F = S₂ ⊕ F₁

F = S₂ ⊕ S₁ ⊕ w

Encoder:

• It is a combinational circuit which converts decimal number into binary number.
• It consists 2ⁿ input lines and n output lines.
• They do not have any select lines.

Additional Information

Decoder:

• It is a combinational circuit which converts binary number into decimal number.
• It consists n input lines and 2ⁿ output lines.
• They also do not have any select lines.

Multiplexer:

• It is a combinational circuit which have many data inputs and single output depending on control or select inputs.​
• For 2^m input lines , m selection lines are required in multiplexer.

De-Multiplexer:

• It is a combinational circuit which have single data input and many data output depending on control or select inputs.​
• For 2^m output lines, m selection lines are required in de-multiplexer.