Memory Address and Capacity MCQ Quiz in मल्याळम - Objective Question with Answer for Memory Address and Capacity - സൗജന്യ PDF ഡൗൺലോഡ് ചെയ്യുക

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നേടുക Memory Address and Capacity ഉത്തരങ്ങളും വിശദമായ പരിഹാരങ്ങളുമുള്ള മൾട്ടിപ്പിൾ ചോയ്സ് ചോദ്യങ്ങൾ (MCQ ക്വിസ്). ഇവ സൗജന്യമായി ഡൗൺലോഡ് ചെയ്യുക Memory Address and Capacity MCQ ക്വിസ് പിഡിഎഫ്, ബാങ്കിംഗ്, എസ്എസ്‌സി, റെയിൽവേ, യുപിഎസ്‌സി, സ്റ്റേറ്റ് പിഎസ്‌സി തുടങ്ങിയ നിങ്ങളുടെ വരാനിരിക്കുന്ന പരീക്ഷകൾക്കായി തയ്യാറെടുക്കുക

Latest Memory Address and Capacity MCQ Objective Questions

Top Memory Address and Capacity MCQ Objective Questions

Memory Address and Capacity Question 1:

Minimum number of bits needed to address 2000 memory location are 

  1. 9
  2. 10
  3. 11
  4. 12

Answer (Detailed Solution Below)

Option 3 : 11

Memory Address and Capacity Question 1 Detailed Solution

The correct option is 3

Concept:

To determine the minimum number of bits needed to address 2000 memory locations, we can calculate the binary logarithm (log base 2) of 2000 and round it up to the nearest integer. This will give us the minimum number of bits required to represent 2000 unique memory locations.

Calculating the binary logarithm of 2000:

log₂(2000) ≈ 10.965784

Rounding up to the nearest integer:

⌈10.965784⌉ = 11

Therefore, the correct answer is 11.

Memory Address and Capacity Question 2:

Codes consisting of light and dark marks which may be optically read is known as-

  1. Mnemonics
  2. Barcode
  3. Decoder
  4. All of these
  5. None of the above

Answer (Detailed Solution Below)

Option 2 : Barcode

Memory Address and Capacity Question 2 Detailed Solution

  • A barcode is a square or rectangular image consisting of a series of parallel black lines and white spaces of varying widths that can be read by a scanner
    • Assembly language is mnemonic code

              Example: MOV A, B

    • In digital electronics, a binary decoder is a combinational logic circuit that converts binary information from the n coded inputs to a maximum of 2n unique outputs

Memory Address and Capacity Question 3:

The size of ROM required to implement a binary multipliers that multiply two 4 bit numbers is

  1. 24 × 4
  2. 28 × 4
  3. 28 × 8
  4. 24 × 7

Answer (Detailed Solution Below)

Option 3 : 28 × 8

Memory Address and Capacity Question 3 Detailed Solution

let 

Then

∴ Number of input bits = 4 + 4 = 8

Number of output = 8 (7 + 1 extra bit for carry)

∴ Size of ROM = 28 × 8

Memory Address and Capacity Question 4:

Which of the following is fastest memory?

  1. Secondary Memory
  2. Auxiliary Memory
  3. Cache Memory
  4. Virtual Memory
  5. None of these

Answer (Detailed Solution Below)

Option 3 : Cache Memory

Memory Address and Capacity Question 4 Detailed Solution

The Correct Answer is "Cache Memory".

Important Points

Cache Memory :

  • Cache Memory is a special very high-speed memory.
  • It is used to speed up and synchronizing with a high-speed CPU. Cache memory is costlier than main memory or disk memory but economical than CPU registers.
  • Cache memory is an extremely fast memory type that acts as a buffer between RAM and the CPU.
  • It holds frequently requested data and instructions so that they are immediately available to the CPU when needed.
  • Cache memory is used to reduce the average time to access data from the Main memory.

Additional Information

Secondary Memory​ :

  • It is non-volatile, i.e. it retains data when power is switched off.
  • It is large capacities to the tune of terabytes.
  • It is cheaper as compared to the primary memory.
  • Depending on whether the Secondary memory device is part of the CPU or not, there are two types of secondary memory – fixed and removable.

                                                        

 Auxiliary Memory :

  • Auxiliary memory is the non-volatile memory lowest-cost, highest-capacity, and slowest-access storage in a computer system.
  • It is where programs and data kept for long-term storage or when not in immediate use.
  • Such memories tend to occur in two types-sequential access (data must access in a linear sequence) and direct access (data may access in any sequence).
  • The most common sequential storage device is the hard disk drives, whereas direct-access devices include rotating drums, disks, CD-ROMs, and DVD-ROMs.
  • It used as permanent storage of data in mainframes and supercomputers.

 

Virtual Memo :

  • A computer can address more memory than the amount physically installed on the system.
  • This extra memory is actually called virtual memory and it is a section of a hard disk that's set up to emulate the computer's RAM.
  • The main visible advantage of this scheme is that programs can be larger than physical memory.
  • Virtual memory serves two purposes.
    • First, it allows us to extend the use of physical memory by using the disk.
    • Second, it allows us to have memory protection because each virtual address is translated to a physical address.

Memory Address and Capacity Question 5:

In microprocessor based systems DMA facility is required to increase the speed of data transfer between the:

  1. Microprocessor and the I/O devices 
  2. Microprocessor and the memory
  3. Memory and the I/O devices 
  4. Memory and the reliability system

Answer (Detailed Solution Below)

Option 3 : Memory and the I/O devices 

Memory Address and Capacity Question 5 Detailed Solution

1. Direct memory access (DMA) is a feature of computer systems that allows certain hardware subsystems to access main system memory (random-access memory), independent of the central processing unit (CPU).

2. DMA avoids using the CPU thus allowing the CPU to attend another job

3. It increases the speed of the data transfer between the memory and the I/O devices

4. DMA is used when a large amount of data is to be printed out from the memory of a computer

5. The problem of slow data transfer between input-output port and memory or between two memory is avoided by implementing the Direct Memory Access (DMA) technique

6. It is implemented by using an 8257 DMA controller

Memory Address and Capacity Question 6:

Consider the following memory interface diagram with an 8085 microprocessor.

The range of addresses 8085 can use to communicate with memory IC.

  1. E000 H to EFFF H only
  2. F000 H to FFFF H only
  3. E000 H to FFFF H only
  4. Either E000 H to EFFF H (or) F000 H to FFFF H.

Answer (Detailed Solution Below)

Option 4 : Either E000 H to EFFF H (or) F000 H to FFFF H.

Memory Address and Capacity Question 6 Detailed Solution

A13, A14 and A15 are connected to NAND gate.

The output of NAND gate should be low to select the chip.

⇒ A13 = A14 = A15 = 1

A12 is not specified.

⇒ A12 = Either 0 (or) 1.

If A12 = 0,

 

Address range = E000 H to EFFF H

Memory Address and Capacity Question 7:

A 16 kb (= 16, 384 bit) memory array is designed as a square with an aspect ratio of one (number of rows is equal to the number of columns). The minimum number of address lines needed for the row decoder is __________.

Answer (Detailed Solution Below) 7

Memory Address and Capacity Question 7 Detailed Solution

The size of a memory register is given by  where  is the number of rows and  is the number of columns. Now, the given memory array is in the size of a square, i.e, the number of rows is equal to the number of columns. Thus, . So, we have .

Now, the rows are fetched by the address lines and all the registers of a particular row are handled by data lines. Now, for a register with 128 flip flops can be handled by  data lines. Similarly, the number of address lines required by the row decoder is also 7.

Memory Address and Capacity Question 8:

An 8 Kbyte ROM with an active low Chip Select input is to be used in an 8085 microprocessor-based system. The ROM should occupy the address range 1000H to 2FFFH. The address lines are designated as 𝐴15 to 𝐴0, where 𝐴15 is the most significant address bit. Which one of the following logic expressions will generate the correct  signal for this ROM?

  1. A15 + A14 + (A 13 . A12 + A̅13 . A̅ 12)
  2. A15 . A14 . (A13 + A12)
  3. 15 . A̅ 14 . (A 13 . A̅12 + A̅13 . A12)
  4. 15 + A̅14 + (A13 . A12)

Answer (Detailed Solution Below)

Option 1 : A15 + A14 + (A 13 . A12 + A̅13 . A̅ 12)

Memory Address and Capacity Question 8 Detailed Solution

Given address range: 1000 H to 2FFF

∴ Total No. of address lines = 13 i.e. 

(1FFF)H = (0001 1111 1111 1111)2 = 13 address lines

i.e.

i.e.

To provide  as low, the condition is

A15 = A14 = 0 and A13 = A12 = (01) or (10)

i.e. A15 = A14 = 0 and A13 , A12 shouldn't be (11) , (00)

Thus it is A15 + A14 + (A 13 . A12 + A̅13 . A̅ 12)

Hence option (1) is correct

Memory Address and Capacity Question 9:

Specify the decimal equivalent of memory content at address 3 in the following figure

The relation between input and output is as follows

  1. 8
  2. 4
  3. 3
  4. 13

Answer (Detailed Solution Below)

Option 2 : 4

Memory Address and Capacity Question 9 Detailed Solution

 

So memory counters address 3 = 0100

∴ Decimal equivalent = 4

address

w

x

y

z

a

b

c

d

0

0

0

0

0

1

0

0

1

1

0

0

0

1

0

0

1

1

2

0

0

1

0

1

0

0

0

3

0

0

1

1

0

1

0

0

4

0

1

0

0

1

1

0

1

5

0

1

0

1

0

0

1

1

6

0

1

1

0

0

0

0

0

7

0

1

1

1

0

0

1

0

8

1

0

0

0

0

0

0

0

9

1

0

0

1

0

0

1

0

15

1

1

1

1

1

0

1

0

Memory Address and Capacity Question 10:

A memory chip has a capacity of 4 kB. How many address lines are required?

  1. 10
  2. 12
  3. 16
  4. 14

Answer (Detailed Solution Below)

Option 2 : 12

Memory Address and Capacity Question 10 Detailed Solution

Explanation:

A memory chip has a capacity of 4 kB. To determine the number of address lines required, we need to understand the relationship between memory capacity and address lines. The capacity of a memory chip is the product of the number of addressable memory locations and the size of each memory location.

Firstly, 4 kB (kilobytes) needs to be converted into bytes. Since 1 kB = 1024 bytes, we have:

4 kB = 4 × 1024 bytes = 4096 bytes

Each memory location in a typical memory chip stores 1 byte of data. Therefore, the memory chip with a capacity of 4096 bytes has 4096 addressable memory locations.

The number of address lines required (n) can be determined using the formula:

Number of addressable memory locations = 2n

Setting this equal to the number of memory locations we have:

2n = 4096

To solve for n, we take the logarithm base 2 of both sides:

n = log2(4096)

Since 4096 is a power of 2 (specifically, 212), we have:

n = 12

Therefore, 12 address lines are required to address 4096 memory locations.

Hence, the correct answer is option 2, which is 12.

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